Recently, for example, the through silicon via (TSV) technique is being developed which aims to increase the capacity and the speed of semiconductor storage devices such as dynamic random access memories (DRAMs) and by which multiple DRAM chips (dice) are stacked on top of one another.
In the TSV technique, small holes are made in chips, and the holes are filled with a metal so that the chips are stacked on top of one another. Thus, these layered chips are electrically connected, and are used as a three-dimensional stack package.
Thus, the TSV technique achieves significant reduction in the wiring distance compared to, for example, a case in which multiple memory chips are connected by wire bonding, and therefore has an advantage in terms of increase in speed, power saving, reduction in size, and the like.
Heretofore, various semiconductor storage devices related to the TSV technique have been proposed.    [Patent document] Japanese Laid-open Patent Publications No. 01-076341    [Patent document] Japanese Laid-open Patent Publications No. 03-282652    [Patent document] Japanese Laid-open Patent Publications No. 04-279949    [Patent document] Japanese Laid-open Patent Publications No. 59-161744    [Patent document] Japanese Laid-open Patent Publications No. 2004-206615
As described above, semiconductor integrated circuits have been recently developed in which the TSV technique is used to achieve an increase in the speed, power saving, a reduction in the size, and the like.
In particular, a semiconductor storage device, such as a DRAM or a synchronous DRAM (SDRAM), has layered memory chips which have a common array of, for example, memory cells, achieving an increase in the speed, power saving, a reduction in the size, and the like along with an increase in the transfer rate.
For example, power supply and heat emission, the method for addressing noise or a defective chip, and the like are important for a semiconductor storage device in which three-dimensional packaging is made by applying the TSV technique. Specifically, for example, when layered memory chips are simultaneously activated and operated, a region of high current and heat occurs, resulting in strict operating conditions for the semiconductor storage device.